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m052/m054 data sheet arm cortex ? -m0 32-bit microcontroller publication release date: mar 15, 2011 - 1 - revision v1.0 numicro ? family m052/m054 data sheet
m052/m054 data sheet publication release date: mar 15, 2011 - 2 - revision v1.0 table of contents 1 general description ????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 6 2 features ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 7 3 block diagram ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 11 4 selection table ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 12 5 pin configuration ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 13 5.1 qfn 33 pin ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 13 5.2 lqfp 48 pin ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 14 5.3 pin description ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 15 6 functional description ????????????????????????????????????????????????????????????????????????????????????????????????????????? 18 6.1 arm? cortex?-m0 core ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 18 6.2 system manager ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 20 6.2.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 20 6.2.2 system reset ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? ? 20 6.2.3 system power architecture ??????????????????????????????????????????????????????????????????????????????????????????????????????? 20 6.2.4 system timer (systick) ????????????????????????????????????????????????????????????????????????????????????????????????????????????? 21 6.2.5 nested vectored interrupt controller (nvic) ?????????????????????????????????????????????????????????????????????????? 22 6.3 clock controller ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 26 6.3.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 26 6.3.2 clock generator block diagram ??????????????????????????????????????????????????????????????????????????????????????????????? 26 6.3.3 system clock & systick clock ????????????????????????????????????????????????????????????????????????????????????????????????? 27 6.3.4 ahb clock source select ?????????????????????????????????????????????????????????????????????????????????????????????????????????? 28 6.3.5 peripherals clock source select ?????????????????????????????????????????????????????????????????????????????????????????????? 28 6.3.6 power down mode (deep sleep mode) clock ??????????????????????????????????????????????????????????????????????? 29 6.3.7 frequency divider output ?????????????????????????????????????????????????????????????????????????????????????????????????????????? 30 6.4 general purpose i/o ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 32 6.4.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 32 6.5 i2c serial interface controller (master/slave) ????????????????????????????????????????????????????????????????????????????????????? 34 6.5.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 34 6.5.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 34 6.6 pwm generator and capture timer ?????????????????????????????????????????????????????????????????????????????????????????????????????? 36 6.6.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 36 6.6.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 37 6.7 serial peripheral interface (spi) controller ?????????????????????????????????????????????????????????????????????????????????????????? 38 6.7.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 38 6.7.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 38 6.8 timer controller ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 39 6.8.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 39 6.8.2 features: ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 39
64 m052/m054 data sheet publication release date: mar 15, 2011 - 3 - revision v1.0 6.9 watchdog timer (wdt) ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 40 6.9.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 40 6.9.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 41 6.10 uart interface controller ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 42 6.10.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 42 6.10.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 44 6.11 analog-to-digital converter (adc) ?????????????????????????????????????????????????????????????????????????????????????????????????????? 45 6.11.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 45 6.11.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 45 6.12 external bus interface (ebi) ????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 47 6.12.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 47 6.12.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 47 6.13 flash memory controller (fmc) ?????????????????????????????????????????????????????????????????????????????????????????????????????????? 48 6.13.1 overview ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 48 6.13.2 features ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 48 7 typical application circuit ?????????????????????????????????????????????????????????????????????????????????????????????????? 49 8 electrical characteristics ???????????????????????????????????????????????????????????????????????????????????????????????? 50 8.1 absolute maximum ratings ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 50 8.2 dc electrical characteristics ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 51 8.3 ac electrical characteristics ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 54 8.3.1 external crystal ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 54 8.3.2 external oscillator ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 54 8.3.3 typical crystal application circuits ?????????????????????????????????????????????????????????????????????????????????????????? 54 8.3.4 internal 22.1184 mhz rc oscillator ????????????????????????????????????????????????????????????????????????????????????????? 55 8.3.5 internal 10khz rc oscillator ????????????????????????????????????????????????????????????????????????????????????????????????????? 55 8.4 analog characteristics ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 56 8.4.1 specification of 600khz sps 12-bit saradc ?????????????????????????????????????????????????????????????????????????? 56 8.4.2 specification of ldo & power management ??????????????????????????????????????????????????????????????????????????? 56 8.4.3 specification of low voltage reset ?????????????????????????????????????????????????????????????????????????????????????????? 57 8.4.4 specification of brownout detector ?????????????????????????????????????????????????????????????????????????????????????????? 57 8.4.5 specification of power-on reset (5v) ????????????????????????????????????????????????????????????????????????????????????? 58 8.5 spi dynamic characteristics ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 59 9 package dimensions ????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 61 9.1 lqfp-48 (7x7x1.4mm 2 footprint 2.0mm) ????????????????????????????????????????????????????????????????????????????????????????????? 61 9.2 qfn-33 (5x5 mm2, thickness 0.8mm, pitch 0.5 mm) ??????????????????????????????????????????????????????????????????????? 62 10 revision history ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 63
m052/m054 data sheet publication release date: mar 15, 2011 - 4 - revision v1.0 list of figures figure 3?1 numicro ? m051 series block diagram ....................................................................... 11 figure 4?1 numicro ? naming rule ............................................................................................... 12 figure 5?1 numicro ? m051 series qf n33 pin diagram .............................................................. 13 figure 5?2 numicro ? m051 series lq fp-48 pin diagram.......................................................... 14 figure 6?1 functional block di agram ............................................................................................ 18 figure 6?2 numicro m051 ? series power arch itecture diagram.................................................. 21 figure 6?3 clock generat or block diagram .................................................................................... 26 figure 6?4 system clo ck block di agram ...................................................................................... 27 figure 6?5 systick clock control blo ck diagram .......................................................................... 27 figure 6?6 ahb clock source for hclk ....................................................................................... 28 figure 6?7 peripheral s clock source se lect for pclk.................................................................. 29 figure 6?8 clock source of frequency divider ............................................................................. 30 figure 6?9 block diagram of frequency divider ........................................................................... 31 figure 6?10 push -pull output................................................................................................... ..... 32 figure 6?11 open-d rain output.................................................................................................. ... 33 figure 6?12 quasi-bidi rectional i/o mode ..................................................................................... 33 figure 6?13 i2c bus timing .......................................................................................................... 34 figure 6?14 timing of in terrupt and re set signal ......................................................................... 41 figure 8?1 typical crystal application circuit ............................................................................... 55 figure 8?2 spi ma ster timing................................................................................................... ...... 60 figure 8?3 spi sl ave timing.................................................................................................... ....... 60
64 m052/m054 data sheet publication release date: mar 15, 2011 - 5 - revision v1.0 list of tables table 4?1 numicro ? m051 series product selecti on guide......................................................... 12 table 5?1 numicro ? m051 series pi n description ....................................................................... 17 table 6?1 exc eption model...................................................................................................... ...... 24 table 6?2 system interrupt map................................................................................................. ... 24 table 6?3 vector table format .................................................................................................. ... 25 table 6?4 watchdog timeout interval selection ........................................................................... 40 table 6?5 uart b aud rate e quation ........................................................................................... 42 table 6?6 uart baud rate setti ng table .................................................................................... 43
m052/m054 data sheet publication release date: mar 15, 2011 - 6 - revision v1.0 1 general description the numicro m051 ? series is a 32-bit microcontroller with embedded arm ? cortex ? -m0 core for industrial control and applications which need rich communication interfaces. the cortex ? -m0 is the newest arm embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. the numicro m051 ? series includes m052, m054, m058 and m0516 families. the m052/m054 can run up to 50 mhz. thus it can afford to sup port a variety of industrial control and applications which need high cpu perfor mance. the m052/m054 has 8k/16k-byte embedded flash, 4k-byte data flash, 4k-byte flash for the isp, and 4k-byte embedded sram. many system level peripheral functions, such as i/o port, ebi (external bus interface), timer, uart, spi, i2c, pwm, adc, watchdog timer and brownout detector, have been incorporated into the m052/m054 in order to reduce compo nent count, board space and system cost. these useful functions make the m052/m054 powe rful for a wide range of applications. additionally, the m052/m054 is equipped with isp (in-system programming) and icp (in-circuit programming) functions, which allow the user to update the program memory without removing the chip from the actual end product.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 7 - revision v1.0 2 features z core ? arm ? cortex ? -m0 core runs up to 50 mhz. ? one 24-bit system timer. ? supports low power sleep-mode. ? a single-cycle 32-bit hardware multiplier. ? nvic for the 32 interrupt inputs, each with 4-levels of priority. ? supports serial wire debug (swd) interface and 2 watchpoints/4 breakpoints. z built-in ldo for wide operati ng voltage range: 2.5v to 5.5v z memory ? 8kb/16kb flash memory for program memory (aprom) ? 4kb flash memory for data memory (dataflash) ? 4kb flash memory for loader (ldrom) ? 4kb sram for internal scratch-pad ram (sram) z clock control ? programmable system clock source ? 4~24 mhz external crystal input ? 22.1184 mhz internal oscillator (trimmed to 1% accuracy) ? 10 khz low-power oscillator for watchdog timer and wake-up in sleep mode ? pll allows cpu operation up to the maximum 50mhz z i/o port ? up to 40 general -purpose i/o (gpio) pins for lqfp-48 package ? four i/o modes: ? quasi bi-direction
m052/m054 data sheet publication release date: mar 15, 2011 - 8 - revision v1.0 ? push-pull output ? open-drain output ? input only with high impendence ? ttl/schmitt trigger input selectable ? i/o pin can be configured as inte rrupt source with edge/level setting ? supports high driver and high sink io mode z timer ? provides four channel 32-bit timers, one 8-bi t pre-scale counter with 24-bit up-timer for each timer. ? independent clock source for each timer. ? 24-bit timer value is readable through tdr (timer data register) ? provides one-shot, periodic and toggle operation modes. z watchdog timer ? multiple clock sources ? supports wake up from power down or sleep mode ? interrupt or reset selectable on watchdog time-out z pwm ? built-in up to four 16-bit pwm generators; providing eight pwm outputs or four complementary paired pwm outputs ? individual clock source, clock divider, 8-bi t pre-scalar and dead-zone generator for each pwm generator ? pwm interrupt synchronized to pwm period ? 16-bit digital capture timers (shared with pwm timers) with rising/falling capture inputs ? supports capture interrupt z uart ? up to two sets of uart device
64 m052/m054 data sheet publication release date: mar 15, 2011 - 9 - revision v1.0 ? programmable baud-rate generator ? buffered receiver and transmitter, each with 15 bytes fifo ? optional flow control function (cts and rts) ? supports irda(sir) function ? supports rs485 function z spi ? up to two sets of spi device. ? supports master/slave mode ? master mode clock rate up to 20 mhz, and slave mode clock rate up to 10 mhz ? full duplex synchronous serial data transfer ? variable length of transfer data from 1 to 32 bits ? msb or lsb first data transfer ? rx latching data can be either at rising edge or at falling edge of serial clock ? tx sending data can be either at rising edge or at falling edge of serial clock ? supports byte suspend mode in 32-bit transmission z i2c ? supports master/slave mode ? bidirectional data transfer between masters and slaves ? multi-master bus (no central master). ? arbitration between simultaneously transmitti ng masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? programmable clocks allow versatile rate control.
m052/m054 data sheet publication release date: mar 15, 2011 - 10 - revision v1.0 ? supports multiple address recognition (f our slave address with mask option) z adc ? 12-bit sar adc with 600k sps ? up to 8-ch single-ended input or 4-ch differential input ? supports single mode/burst mode/single -cycle scan mode/continuous scan mode ? each channel with an individual result register ? supports conversion value monitoring (or comparison) for threshold voltage detection ? conversion can be started either by soft ware trigger or external pin trigger z ebi (external bus interface) for external memory-mapped device access ? accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode ? supports 8-bit/16-bit data width z in-system programming (isp) and in-circuit programming (icp) z brownout detector ? with 4 levels: 4.5v/3.8v/2.7v/2.2v ? supports brownout interrupt and reset option z lvr (low voltage reset) ? threshold voltage levels: 2.0v z operating temperature: -40 ~85 z packages: ? green package (rohs) ? 48-pin lqfp, 33-pin qfn
64 m052/m054 data sheet publication release date: mar 15, 2011 - 11 - revision v1.0 3 block diagram figure 3?1 numicro ? m051 series block diagram
m052/m054 data sheet publication release date: mar 15, 2011 - 12 - revision v1.0 4 selection table numicro m051? series selection guide connectivity part no. aprom ram data flash ldrom i/o timer uart spi i2c pwm adc ebi isp icp package m052lan 8kb 4kb 4kb 4kb 40 4x32-bit 2 2 1 8 8x12-bit v v lqfp48 m052zan 8kb 4kb 4kb 4kb 24 4x32-bit 2 1 1 5 5x12-bit v qfn 33 M054LAN 16kb 4kb 4kb 4kb 40 4x32-bit 2 2 1 8 8x12-bit v v lqfp48 m054zan 16kb 4kb 4kb 4kb 24 4x32-bit 2 1 1 5 5x12-bit v qfn 33 table 4?1 numicro ? m051 series product selection guide m0 5x -x x x arm cortex-m0 l : lqfp 48 z : qfn 33 52 : 8k flash rom 54 : 16k flash rom - cpu core reserved part number temperature package -40 ~ +105 e: -40 ~ +85 n: -40 ~ +105 c: figure 4?1 numicro m051 ? naming rule
64 m052/m054 data sheet publication release date: mar 15, 2011 - 13 - revision v1.0 5 pin configuration 5.1 qfn 33 pin figure 5?1 numicro ? m051 series qfn33 pin diagram
m052/m054 data sheet publication release date: mar 15, 2011 - 14 - revision v1.0 5.2 lqfp 48 pin figure 5?2 numicro ? m051 series lqfp-48 pin diagram
64 m052/m054 data sheet publication release date: mar 15, 2011 - 15 - revision v1.0 5.3 pin description pin number alternate function qfn33 lqfp48 symbol 1 2 type [1] description 11 16 xtal1 i (st) crystal1: this is the input pin to the internal inverting amplifier. the system clock is from external crystal or resonator when fosc[1:0] (config3[1:0]) are both logic 1 by default. 10 15 xtal2 o crystal2: this is the output pin from the internal inverting amplifier. it emits the inverted signal of xtal1. 27 41 vdd p power supply: supply voltage digital v dd for operation. 12 33 17 vss p ground: digital ground potential. 28 42 avdd p power supply: supply voltage analog av dd for operation. 4 6 avss p ground: analog ground potential. 13 18 ldo_c ap p ldo: ldo output pin note: it needs to be connected with a 10uf capacitor. 2 4 /rst i (st) reset: /rst pin is a schmitt trigger input pin for hardware device reset. a ? low? on this pin for 768 clock counter of internal rc 22.1184 mhz while the system clock is running will reset the device. /rst pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to gnd. 26 40 p0.0 cts1 ad0 d, i/o 25 39 p0.1 rts1 ad1 d, i/o nc 38 p0.2 cts0 ad2 d, i/o nc 37 p0.3 rts0 ad3 d, i/o 24 35 p0.4 spiss1 ad4 d, i/o port0: port 0 is an 8-bit four mode output pin and two mode input. its multifunction pins are for cts1, rts1, cts0, rts0, spiss1, mosi_1, miso_1, and spiclk1. p0 has an alternative function as ad[7:0] while external memory interface (ebi) is enabled. these pins which are spiss1, mosi_1, miso_1, and spiclk1 for the spi function used. cts0/1: clear to send input pin for uart0/1
m052/m054 data sheet publication release date: mar 15, 2011 - 16 - revision v1.0 pin number alternate function qfn33 lqfp48 symbol 1 2 type [1] description 23 34 p0.5 mosi_1 ad5 d, i/o 22 33 p0.6 miso_1 ad6 d, i/o 21 32 p0.7 spiclk1 ad7 d, i/o rts0/1: request to send output pin for uart0/1 29 43 p1.0 t2 ain0 i/o nc 44 p1.1 t3 ain1 i/o 30 45 p1.2 rxd1 ain2 i/o 31 46 p1.3 txd1 ain3 i/o 32 47 p1.4 spiss0 ain4 i/o 1 1 p1.5 mosi_0 ain5 i/o nc 2 p1.6 miso_0 ain6 i/o nc 3 p1.7 spiclk0 ain7 i/o port1: port 1 is an 8-bit four mode output pin and two mode input. its multifunction pins are for t2, t3, rxd1, txd1, spiss0, mosi_0, miso_0, and spiclk0. t2: timer2 external input t3: timer3 external input these pins which are spiss0, mosi_0, miso_0, and spiclk0 for the spi function used. these pins which are ain0 ~ain7 for the 12 bits adc function used. the rxd1/txd1 pins are for uart1 function used. nc 19 p2.0 pwm0 ad8 d, i/o nc 20 p2.1 pwm1 ad9 d, i/o 14 21 p2.2 pwm2 ad10 d, i/o 15 22 p2.3 pwm3 ad11 d, i/o 16 23 p2.4 pwm4 ad12 d, i/o 17 25 p2.5 pwm5 ad13 d, i/o 18 26 p2.6 pwm6 ad14 d, i/o nc 27 p2.7 pwm7 ad15 d, i/o port2: port 2 is an 8-bit four mode output pin and two mode input. it has an alternative function p2 has an alternative function as ad[15:8] while external memory interface (ebi) is enabled. these pins which are pwm0~pwm7 for the pwm function. 3 5 p3.0 rxd i/o 5 7 p3.1 txd i/o port3: port 3 is an 8-bit four mode output pin and two mode input. its multifunction pins are for rxd, txd, 0int ,
64 m052/m054 data sheet publication release date: mar 15, 2011 - 17 - revision v1.0 pin number alternate function qfn33 lqfp48 symbol 1 2 type [1] description 6 8 p3.2 0int stadc i/o nc 9 p3.3 1int mclk i/o 7 10 p3.4 t0 sda i/o 8 11 p3.5 t1 scl i/o 9 13 p3.6 wr cko i/o nc 14 p3.7 rd i/o 1int , t0, t1, wr , and rd . t0: timer0 external input t1: timer1 external input the rxd/txd pins are for uart0 function used. the sda/scl pins are for i2c function used. mclk: ebi clock output pin. cko: hclk clock output the stadc pin is for adc external trigger input. nc 24 p4.0 pwm0 i/o nc 36 p4.1 pwm1 i/o nc 48 p4.2 pwm2 i/o nc 12 p4.3 pwm3 i/o nc 28 p4.4 /cs i/o nc 29 p4.5 ale i/o 19 30 p4.6 ice_clk i/o 20 31 p4.7 ice_dat i/o port4: port 4 is an 8-bit four mode output pin and two mode input. its multifunction pins are for /cs, ale, ice_clk and ice_dat. /cs for ebi (external bus interface) used. ale (address latch enable) is used to enable the address latch that separates the address from the data on port 0 and port 2. the ice_clk/ice_dat pins are for jtag-ice function used. pwm0-3 can be used from p4.0-p4.3 when ebi is active. table 5?1 numicro ? m051 series pin description [1] i/o type description. i: input, o: output, i/o: quasi bi-direction, d: open- drain, p: power pins, st: schmitt trigger.
m052/m054 data sheet publication release date: mar 15, 2011 - 18 - revision v1.0 6 functional description 6.1 arm? cortex?-m0 core the cortex ? -m0 processor is a configurable, multistage, 32-bit risc processor. it has an amba ahb- lite interface and includes an nvic component. it al so has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex-m profile processor. the profile supports two modes -thread and handler modes. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 6?1 functional block diagram the implemented device provides: a low gate count processor the features: ? the armv6-m thumb ? instruction set. ? thumb-2 technology. ? armv6-m compliant 24-bit systick timer. ? a 32-bit hardware multiplier. ? the system interface supports little-endian data accesses. ? the ability to have deterministic, fixed-latency, interrupt handling.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 19 - revision v1.0 ? load/store-multiples and multicycle-multip lies that can be abandoned and restarted to facilitate rapid interrupt handling. ? c application binary interface compliant exception model. this is the armv6-m, c application binary in terface(c-abi) compliant exception model that enables the use of pure c functions as interrupt handlers. ? low power sleep-mode entry using wait for interrupt (wfi), wait for event(wfe) instructions, or the return from interrupt sleep-on-exit feature. nvic features: ? 32 external interrupt inputs, each with four levels of priority. ? dedicated non-maskable interrupt (nmi) input. ? support for both level-sensitive and pulse-sensitive interrupt lines ? wake-up interrupt controller (wic), supports ultra-low power sleep mode. debug support: ? four hardware breakpoints. ? two watchpoints. ? program counter sampling register (pcs r) for non-intrusive code profiling. ? single step and vector catch capabilities. bus interfaces: ? single 32-bit amba-3 ahb-lite system interfac e that provides simple integration to all system peripherals and memory. ? single 32-bit slave port that s upports the dap (debug access port).
m052/m054 data sheet publication release date: mar 15, 2011 - 20 - revision v1.0 6.2 system manager 6.2.1 overview the following functions are included in system manager section ? system resets ? system memory map ? system management registers for part number id, chip reset and on-chip module reset , multi-functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registers 6.2.2 system reset the system reset includes one of the list below event occurs. for these reset event flags can be read by rstrc register. ? the power-on reset (por) ? the low level on the /reset pin ? watchdog time out reset (wdt) ? low voltage reset (lvr) ? brownout-detected reset (bod) ? cpu reset ? system reset 6.2.3 system power architecture in this device, the power architec ture is divided into two segments. ? analog power from avdd and avss provides the power for analog module operation. ? digital power from vdd and vss supplies t he power to the internal regulator which provides a fixed 2.5v power for digital operation and i/o pins. the outputs of internal voltage regulator, which is ldo, require an external capacitor which should be located close to the corresponding pin. the figure 6?2 shows the power architecture of this device.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 21 - revision v1.0 5v to 2.5v ldo pll 12-bit sar-adc brown out detector por50 por25 low voltage reset flash digital logic ( timer/uart/i2c/spi? ) 2.5v irc 22.1184mhz & 10khz osc. avdd avss vdd vss ldo_cap 10uf io cell p0~p4 vss numicro-m051 po wer architecture figure 6?2 numicro m051 ? series power architecture diagram 6.2.4 system timer (systick) the cortex-m0 includes an integrated system time r, systick. systick provides a simple, 24-bit clear-on-write, decrementing, wr ap-on-zero counter with a flexible control mechanism. the counter can be used as a real time operating sy stem (rtos) tick timer or as a simple counter. when system timer is enabled, it will count dow n from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock edge, t hen decrement on subseque nt clocks. when the counter transitions to zero, the countflag stat us bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value
m052/m054 data sheet publication release date: mar 15, 2011 - 22 - revision v1.0 rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?. 6.2.5 nested vectored interrupt controller (nvic) cortex-m0 provides an interrupt c ontroller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: z nested and vectored interrupt support z automatic processor state saving and restoration z dynamic priority changing z reduced and deterministic interrupt latency the nvic prioritizes and handles all supported ex ceptions. all exceptions are handled in ?handler mode?. this nvic architecture su pports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will com pare the priority of t he new interrupt to the current running one?s priority. if the priority of t he new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting addr ess of the interrupt se rvice routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlat ed isr by software. while the starting address is fetched, nvic will also automatically save proc essor state including the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume t he normal execution. thus it will ta ke less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back-to-back interrupts e fficiently without the overhead of states saving and restoration and t herefore reduces delay time in switching to pending isr at the end of current isr. the nvic al so supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher prio rity interrupt request oc curs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penal ty. thus it advances the real-time capability. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 23 - revision v1.0 6.2.5.1 exception model and system interrupt map the table 6?1 lists the exception model supported by numicro m051 ? series. software can set four levels of priority on some of these exceptio ns as well as on all interrupts. the highest user- configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user-configurable interrupts is ?0?. note t hat priority ?0? is treated as the fourth priority on the system, after three system except ions ?reset?, ?nmi? and ?hard fault?. exception number vector address interrupt number (bit in interrupt registers) interrupt name source ip interrupt description power down wakeup 1-15 0x00-0x3c - - - system exceptions 16 0x40 0 bod_out brownou t brownout low voltage detected interrupt yes 17 0x44 1 wdt_int wdt watch dog timer interrupt yes 18 0x48 2 eint0 gpio external signal interrupt from p3.2 pin yes 19 0x4c 3 eint1 gpio external signal interrupt from p3.3 pin yes 20 0x50 4 gp01_int gpio external signal interrupt from p0[7:0] / p1[7:0] yes 21 0x54 5 gp234_int gpio external interrupt from p2[7:0]/p3[7:0]/p4[7:0], except p32 and p33 yes 22 0x58 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt no 23 0x5c 7 pwmb_int pwm4~7 pwm4, pwm5, pwm6 and pwm7 interrupt no 24 0x60 8 tmr0_int tmr0 timer 0 interrupt no 25 0x64 9 tmr1_int tmr1 timer 1 interrupt no 26 0x68 10 tmr2_int tmr2 timer 2 interrupt no 27 0x6c 11 tmr3_int tmr3 timer 3 interrupt no 28 0x70 12 uart0_int uart0 uart0 interrupt yes 29 0x74 13 uart1_int uart1 uart1 interrupt yes
m052/m054 data sheet publication release date: mar 15, 2011 - 24 - revision v1.0 30 0x78 14 spi0_int spi0 spi0 interrupt no 31 0x7c 15 spi1_int spi1 spi1 interrupt no 32-33 0x80-0x84 16-17 - - - - 34 0x88 18 i2c_int i2c i2c interrupt no 35-43 0x8c- 0xac 19-27 - - - - 44 0xb0 28 pwrwu_int clkc clock controller interrupt for chip wake up from power-down state yes 45 0xb4 29 adc_int adc adc interrupt no 46-47 0xb8- 0xbc 30-31 - - - table 6?1 exception model e e x x c c e e p p t t i i o o n n n n a a m m e e v v e e c c t t o o r r n n u u m m b b e e r r p p r r i i o o r r i i t t y y reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 6?2 system interrupt map 6.2.5.2 vector table when any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6-m, the vector table base address is fixed at 0x00000000. t he vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in t he vector table associated with exception handler
64 m052/m054 data sheet publication release date: mar 15, 2011 - 25 - revision v1.0 entry as illustrated in previous section. vector table word offset description 0 sp_main ? the main stack pointer vector number exception entry po inter using that vector number table 6?3 vector table format 6.2.5.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set- enable or interrupt clear-enable r egister bit-field. the registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled stat e of the corresponding interrupts. when an interrupt is disabled, interr upt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by rese t or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the se t-pending register and clear-pending register respectively. the registers use a write-1-to-en able and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear-pending register has no effect on the execut ion status of an active interrupt. nvic interrupts are prioritized by updating an 8-bi t field within a 32-bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessibl e from a block of memory in the system control space and will be described in next section.
m052/m054 data sheet publication release date: mar 15, 2011 - 26 - revision v1.0 6.3 clock controller 6.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also im plements the power control function with the individually clock on/off control, clock source selection and a 4-bit clock divider. the chip will not enter power-down mode until cpu sets the power down enable bit (pwr_down_en) and cortex-m0 core executes the wfi instruction. after that, chip enter power-down mode and wait for wake-up interrupt source triggered to leave power-down mode. in the power down mode, the clock controller turns off the external crystal and internal 22.1184 mhz oscillator to reduce the overall system power consumption. 6.3.2 clock generator block diagram the clock generator consists of 4 sources which list below: z one external 4~24 mhz crystal z one internal 22.1184 mhz rc oscillator z one programmable pll fout(pll source consists of external 4~24 mhz crystal and internal 22.1184m) z one internal 10 khz oscillator xt_out external crystal 4~24m xtl12m_en(pwrcon[0]) xt_in internal osc22m 22.1184m osc22m_en(pwrcon[2]) 0 1 pll pll_src(pllcon[19]) pll fout osc10k 10k osc10k_en(pwrcon[3]) 4~24m 22.1184m 10k figure 6?3 clock generator block diagram
64 m052/m054 data sheet publication release date: mar 15, 2011 - 27 - revision v1.0 6.3.3 system clock & systick clock the system clock has 4 clock sources which we re generated from clock generator block. the clock source switch depends on the register hclk_s(clksel0[ 2:0]). the bloc k diagram is shown in the figure 6?4. figure 6?4 system clock block diagram the clock source of systick in cortex-m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the sy stick clock (stclk) has 4 clock sources. the clock source switch depends on the setting of t he register stclk_s (clksel0[5:3]. the block diagram is shown in the figure 6?5. figure 6?5 systick clock control block diagram
m052/m054 data sheet publication release date: mar 15, 2011 - 28 - revision v1.0 6.3.4 ahb clock source select isp_en (ahbclk[2]) hclk isp (in system programmer) ebi_en (ahbclk[3]) hclk ebi (external bus interface) figure 6?6 ahb clock source for hclk 6.3.5 peripherals clock source select the peripherals clock had different clock source switch setting which depends on the different peripheral. please refer the clksel1 & apbclk register description in chapter 6.3.9.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 29 - revision v1.0 w dt_en (apbclk1[0]) pclk w atch dog tim er tim er1 tim er0 tmr0_en (apbclk1[2]) tmr1_en (apbclk1[3]) tim er2 tmr2_en (apbclk1[4]) tim er3 tmr3_en (apbclk1[5]) frequency divider fdiv_en (apbclk1[6]) i2 c i2c0_en (apbclk1[8]) spi0 spi0_en (apbclk1[12]) spi1 spi1_en (apbclk1[13]) uart0 uart0_en (apbclk1[16]) uart1 uart1_en (apbclk1[17]) pw m01 pw m 01_en (apbclk 1[20]) pw m23 pw m23_en (apbclk1[21]) pw m45 pw m45_en (apbclk1[22]) pw m67 pw m67_en (apbclk1[23]) figure 6?7 peripherals clock source select for pclk 6.3.6 power down mode (deep sleep mode) clock when chip enter into power down mode, most of clock sources, perip heral clocks and system clock will be disabled. some of clock sources and periph erals clock are still active in power down mode. for theses clocks which still keep active list below:
m052/m054 data sheet publication release date: mar 15, 2011 - 30 - revision v1.0 clock generator ? internal 10 khz oscillator clock ? peripherals clock (when these ip adopt 10 khz as clock source) ? watch dog clock ? timer 0/1/2/3 clock ? pwm clock 6.3.7 frequency divider output this device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to p3.6. therefore there are 16 options of power-of-2 divided clocks with the frequency from f in /2 1 to f in /2 17 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4-bit value in freqdiv.fsel[3:0]. when write 1 to divider_en (frq div[4]), the chained counter starts to count. when write 0 to divider_en (frqdiv[4]), the c hained counter continuously runs till divided clock reaches low state and stay in low state. 11 10 00 hclk ext. crystal 22.1184m clksel2.frqdiv_s[3:2] apbclk.frqdiv_en[6] frqdiv_clk figure 6?8 clock source of frequency divider
64 m052/m054 data sheet publication release date: mar 15, 2011 - 31 - revision v1.0 16 chained divide-by-2 counter 1/2 ?... 1/2 2 1/2 3 1/2 1 5 1/2 1 6 000 001 110 111 freqdiv.fsel[3:0] : : 16 to 1 mux freqdiv.fdiv_en[4] 0 to 1 reset clock divider 10 00 p3_alt[6] p3_mfp[6] p3.6/clko p3_dout[6] frqdiv_clk figure 6?9 block diagram of frequency divider
m052/m054 data sheet publication release date: mar 15, 2011 - 32 - revision v1.0 6.4 general purpose i/o 6.4.1 overview there are 40 general purpose i/o pins shared with special feature functions in this mcu. the 40 pins are arranged in 5 ports named with p0, p1, p2, p3 and p4. each port equips maximum 8 pins. each one of the 40 pins is independent and has the corresponding register bits to control the pin mode function and data the i/o type of each of i/o pins can be softw are configured individually as input, output, open- drain or quasi-bidirectional mode. the all pins of i/o type stay in quasi-bidirectional mode and port data register px_dout[7:0] resets to 0x000_00ff. each i/o pin equips a very weakly individual pull-up resistor which is about 110k ~300k for v dd is from 5.0v to 2.5v. 6.4.1.1 input mode explanation set px_pmd (pmdn[1:0]) to 00b the px[n] pin is in input mode and the i/o pin is in tri-state(high impedance) without output drive capability. the px_pin value reflects t he status of the corresponding port pins. 6.4.1.2 output mode explanation set px_pmd (pmdn[1:0]) to 2?b01 the px[n] pin is in ou tput mode and the i/o pin supports digital output function with source/sink cu rrent capability. the bit value in the corresponding bit [n] of px_dout is driven on the pin. port pin input data port latch data p n vdd figure 6?10 push-pull output 6.4.1.3 open-drain mode explanation set px_pmd (pmdn[1:0]) to 2?b10 the px[n] pin is in open-drain mode and the i/o pin supports digital output function but only with sink curren t capability, an additional pull-up resister is needed for driving high state. if the bit value in the corr esponding bit [n] of px_dout is ?0?, the pin drive a ?low? output on the pin. if the bit value in the co rresponding bit [n] of px_dout is ?1?, the pin output drives high that is contro lled by the internal pull-up resistor or the external pull high resistor.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 33 - revision v1.0 port pin port latch data n input data figure 6?11 open-drain output 6.4.1.4 quasi-bidirectional mode explanation set px_pmd (pmdn[1:0]) to 2?b11 the px[n] pin is in quasi-bidirectional mode and the i/o pin supports digital output and input function at the sa me time but the source current is only up to hundreds ua. before the digital input function is performed the corresponding bit in px_dout must be set to 1. the quasi-bidirectional out put is common on the 80c51 and most of its derivatives. if the bit value in the corresponding bit [n] of px_dout is ?0?, the pin drive a ?low? output on the pin. if the bit value in the corresp onding bit [n] of px_dout is ?1?, the pin will check the pin value. if pin value is high, no action takes. if pin state is low, then pin will drive strong high with 2 clock cycles on the pin and then disable t he strong output drive and then the pin status is control by internal pull-up resistor. note that the source current capability in quasi-bidirectional mode is only about 200ua to 30ua for vdd is form 5.0v to 2.5v port pin 2 cpu clock delay input data port latch data pp p n vdd strong very weak weak figure 6?12 quasi-bidirectional i/o mode
m052/m054 data sheet publication release date: mar 15, 2011 - 34 - revision v1.0 6.5 i2c serial interface controller (master/slave) 6.5.1 overview i2c is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. the i2c standard is a true multi-master bus including collision detection and arbitration that prevents data corrupt ion if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte-by-byte basis. each data byte is 8 bits long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the figure 6?13 for m ore detail i2c bus timing. t buf stop sda scl start t hd;sta t low t hd;dat t high t f t su;dat repeated start t su;sta t su;sto stop t r figure 6?13 i2c bus timing the device?s on-chip i2c provides the serial interface that meets the i2c bus standard mode specification. the i2c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i2c h/w interfaces to the i2c bus via two pins: sda (px.y, serial data line) and scl (px.y, serial clock lin e). pull up resistor is needed for pin px.y and px.y for i2c operation as these are open drain pins. when the i/o pins are used as i2c port, user must set the pins function to i2c in advance. 6.5.2 features the i2c bus uses two wires (sda and scl) to tr ansfer information between devices connected to the bus. the main featur es of the bus are: ? support master and slave mode ? bidirectional data transfer between masters and slaves ? multi-master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus
64 m052/m054 data sheet publication release date: mar 15, 2011 - 35 - revision v1.0 ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? built-in a 14-bit time-out counter will reque st the i2c interrupt if the i2c bus hangs up and timer-out counter overflows. ? external pull-up are needed for high output ? programmable clocks allow versatile rate control ? supports 7-bit addressing mode ? i2c-bus controllers support multiple address recognition ( four slave address with mask option)
m052/m054 data sheet publication release date: mar 15, 2011 - 36 - revision v1.0 6.6 pwm generator and capture timer 6.6.1 overview numicro m051 ? series has 2 sets of pwm group supports 4 sets of pwm generators which can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable dead-zone generators. each pwm generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16-bit pwm down- counters for pwm period control, two 16-bit comparators for pwm duty control and one dead- zone generator. the 4 sets of pwm generator s provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one-shot mode to produce only one pwm cycle signal or auto-reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perf orm complementary pwm paired function; the paired pwm timing, period, duty and dead-time ar e determined by pwm0 timer and dead-zone generator 0. similarly, the complementary pw m pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead-zone generator 2, 4 and 6, respectively. refer to figures bellowed for the architecture of pwm timers. to prevent pwm driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching ze ro. the double buffering feature avoids glitch at pwm outputs. when the 16-bit period down counter reaches ze ro, the interrupt request is generated. if pwm- timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm-timer is set as one-shot mode, the down count er will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down-counter value matches the value of compare register. the alternate feature of the pwm-timer is digita l input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm 0; and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm-timer before ena ble capture feature. a fter capture feature is enabled, the capture always latched pwm-counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm-counter to capture falling latch register (cflr) when input channel has a fallin g transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ie0[1 ] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 37 - revision v1.0 capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capture channel 0 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr0 and ccr2 . for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0/ 1/2/3 will be reload at this moment. the maximum captured frequency that pwm can c apture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at l east three steps, they are: read piirx to get interrupt source and read pwm_cr lx/pwm_cflx(x=0 and 3) to get capture value and finally write 1 to clear piirx. if interrupt late ncy will take time t0 to finish, the capture signal mustn?t transition during this interval (t0). in this case, the maximum capture frequency will be 1/t0. for example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will is 1/900ns 1000 khz 6.6.2 features 6.6.2.1 pwm function features: pwm group has two pwm generators. each pwm generator supports one 8-bit prescaler, one clock divider, two pwm-timers (down counter ), one dead-zone generator and two pwm outputs. ? up to 16 bits resolution ? pwm interrupt request synchronized with pwm period ? one-shot or auto-reload mode pwm ? up to 2 pwm group (pwma/pwmb) to support 8 pwm channels 6.6.2.2 capture function features: ? timing control logic shar ed with pwm generators ? 8 capture input channels shared with 8 pwm output channels ? each channel supports one rising latch regi ster (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
m052/m054 data sheet publication release date: mar 15, 2011 - 38 - revision v1.0 6.7 serial peripheral interface (spi) controller 6.7.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4-wire bi-direction interface. numicro m051 ? series contains up to two sets of spi controller performing a serial-to- parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. each set of spi controller can be set as a master; it also can be configured as a slave device controlled by an off-chip master device. 6.7.2 features z up to two sets of spi controller z support master or slave mode operation z configurable bit length up to 32 bits of a tr ansfer word and configurable word numbers up to 2 of a transaction, so the maximum bit length is 64 bits for each data transfer z provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer z support msb or lsb first transfer z byte or word suspend mode z variable output serial clock frequency in master mode z support two programmable serial clock frequencies in master mode
64 m052/m054 data sheet publication release date: mar 15, 2011 - 39 - revision v1.0 6.8 timer controller 6.8.1 overview the timer controller includes four 32-bit timers , timer0~timer3, which allows user to easily implement a timer control for applications. the timer can perform functions like frequency measurement, interval measurement, clock generat ion, delay timing, and so on. the timer can generates an interrupt signal upon timeout, or provide the current value of count during operation. 6.8.2 features: ? provides four channels of 32-bit timers with one 8-bit pre-scale counter with four 24-bit up- timer ? independent clock source for each timer. ? 24-bit timer value is readable through tdr (timer data register) ? provides one-shot, periodic and toggle operation modes.
m052/m054 data sheet publication release date: mar 15, 2011 - 40 - revision v1.0 6.9 watchdog timer (wdt) 6.9.1 overview the purpose of watchdog timer is to perform a sy stem reset when system runs into an unknown state. this prevents sy stem from hanging for an infinite period of time. besides, this watchdog timer supports another function to wakeup cpu from power-down mode. the watchdog timer includes a 18-bit free running counter with programmable time-out intervals. table 6?4 shows the watchdo g timeout interval selection and figure 6?14 shows the timing of watchdog interrupt sign al and reset signal. setting wte (wdtcr [7]) enables the watchdog ti mer and the wdt counter starts counting up. when the counter reaches the selected time-out interval, watchdog timer interrupt flag wtif will be set immediately to request a wdt interrupt if the watchdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time-out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to reset the 18-bit wdt counter to avoid cpu from watchdog timer reset before the delay time expires. wtr bit is cl eared automatically by hardware after wdt counter is reset. there are eight time-out intervals with specific delay time which are selected by watchdog timer interval select bits wtis (wdt cr [10:8]). if the wdt counter has not been cleared after the specific delay time expires, t he watchdog timer will set watchdog timer reset flag (wtrf) high and reset cpu. this reset will last 63 wdt clocks (t rst ) then cpu restarts executing program from reset vector (0x0000 0000). wtrf will not be cleared by watchdog reset. user may poll wtfr by software to recognize the reset source. wdt also provides wakeup function. when chip is powered down and the watchdog timer wakeup function enable bit (wdtr[4]) is set, if the wd t counter has not been cleared after the specific delay time expires, the chip will be waken up from power down state. wtis timeout interval selection t tis interrupt period t int wtr timeout interval (wdt_clk=10 khz) min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t wdt 1024 * t wdt 26.2144 s ~ 26.3168 s table 6?4 watchdog timeout interval selection
64 m052/m054 data sheet publication release date: mar 15, 2011 - 41 - revision v1.0 figure 6?14 timing of interrupt and reset signal 6.9.2 features ? 18-bit free running counter to avoid cpu from watchdog timer reset before the delay time expires. ? selectable time-out interval (2^4 ~ 2^18) and the time out interval is 1.6 ms ~ 26.21 s (if wdt_clk = 10 khz). ? reset period = wdt_clk * 63
m052/m054 data sheet publication release date: mar 15, 2011 - 42 - revision v1.0 6.10 uart interface controller numicro m051 ? series provides up to two channels of universal asynchronous receiver/transmitters (uart). uart0~1 perf orms normal speed uart, and support flow control function. 6.10.1 overview the universal asynchronous receiver/transmitter (uart) performs a serial-to-parallel conversion on data received from the periphera l, and a parallel-to-serial conversion on data transmitted from the cpu. the uart controlle r also supports irda sir function, and rs-485 mode functions. each uart channel supports five types of interrupts including transmitter fifo empty interrupt (int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (parity error or framing error or brea k interrupt) (int_rls), receiver buffer time out interrupt (int_tout), and modem/wakeup status interrupt (int_modem). interrupt number 12 (vector number is 28) supports uart0 interrup t. interrupt number 13 (vector number is 29) supports uart1 interrupt. refer to nested vect ored interrupt controller chapter for system interrupt map. the uart0~1 are equipped 15-bytes transmitter fifo (tx_fifo) and 15-bytes receiver fifo (rx_fifo). the cpu can read the status of t he uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 3 error condi tions (parity error, framing error, and break interrupt) probably occur while receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. the baud rate e quation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). the table 6?5 and table 6?6 list the equations in the various c onditio ns and the uart baud rate setting table. mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 6?5 uart baud rate equation
64 m052/m054 data sheet publication release date: mar 15, 2011 - 43 - revision v1.0 system clock = 22.1184 mhz baud rate mode0 mode1 mode2 921600 x a=0,b=11 a=22 460800 a=1 a=1,b=15 a=2,b=11 a=46 230400 a=4 a=4,b=15 a=6,b=11 a=94 115200 a=10 a=10,b=15 a=14,b=11 a=190 57600 a=22 a=22,b=15 a=30,b=11 a=382 38400 a=34 a=62,b=8 a=46,b=11 a=34,b=15 a=574 19200 a=70 a=126,b=8 a=94,b=11 a=70,b=15 a=1150 9600 a=142 a=254,b=8 a=190,b=11 a=142,b=15 a=2302 4800 a=286 a=510,b=8 a=382,b=11 a=286,b=15 a=4606 table 6?6 uart baud rate setting table the uart0 and uart1 controllers support auto-flow control function that uses two low-level signals, /cts (clear-to-send) and /rts (request- to-send), to control the flow of data transfer between the uart and external devices (ex: mode m). when auto-flow is enabled, the uart is not allowed to receive data until the uart assert s /rts to external dev ice. when the number of bytes in the rx fifo equals the value of rt s_tri_lev (ua_fcr [19:16]), the /rts is de- asserted. the uart sends data out when uart cont roller detects /cts is asserted from external device. if a valid asserted /cts is not detected the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) function (user must set irda_en (ua_fun_sel[1:0]) to enable irda function). the sir specification defines a short- range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex ). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half-duplex onl y. so it cannot transmit and receive data at the same time. the irda sir phy sical layer specifies a minimum 10ms transfer delay between transmission and reception. this del ay feature must be implemented by software.
m052/m054 data sheet publication release date: mar 15, 2011 - 44 - revision v1.0 another alternate function of uart controllers is rs-485 9 bit mode function, and direction control provided by rts pin or can program gpio (p0.3 for rts0 and p0.1 for rts 1) to implement the function by software. the rs-485 mode is selected by setting the ua_fun_sel register to select rs-485 function. the rs- 485 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. in rs-485 mode, many characteristics of the rx and tx are same as uart. 6.10.2 features ? full duplex, asynchronous communications ? separate receive / transmit 15 bytes (uar t0/uart1) entry fifo for data payloads ? support hardware auto flow control/flow c ontrol function (cts, rts) and programmable rts flow control trigger level (uart0 and uart1 support) ? programmable receiver buffer trigger level ? support programmable baud-rate generator for each channel individually ? support cts wake up function (uart0 and uart1 support) ? support 7 bit receiver buffer time out detection function ? programmable transmitting data delay time betwe en the last stop and the next start bit by setting ua_tor [dly] register ? support break error, frame erro r, and parity error detect function ? fully programmable serial-interface characteristics ? programmable number of data bit, 5, 6, 7, 8 bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation ? support irda sir function mode ? support for 3/16 bit duration for normal mode ? support rs-485 function mode. ? support rs-485 9bit mode ? support hardware or software direct enable control provided by rts pin
64 m052/m054 data sheet publication release date: mar 15, 2011 - 45 - revision v1.0 6.11 analog-to-digital converter (adc) 6.11.1 overview numicro m051 ? series contain one 12-bit successive appr oximation analog-to-digital converters (sar a/d converter) with 8 input channels. t he a/d converter supports four operation modes: single, burst, single-cycle scan a nd continuous scan mode. the a/d converters can be started by software and external stadc/p3.2 pin. 6.11.2 features ? analog input voltage range: 0~avdd (max to 5.0v). ? 12-bit resolution and 10-bit accuracy is guaranteed. ? up to 8 single-end analog input channels or 4 differential analog input channels. ? maximum adc clock frequency is 16 mhz. ? up to 600k sps conversion rate. ? four operating modes - single mode: a/d conversion is performed one time on a specified channel. - single-cycle scan mode: a/ d conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel. - continuous scan mode: a/d converter cont inuously performs single-cycle scan mode until software stops a/d conversion. - burst mode: a/d conversion will sample and convert the specified single channel and sequentially store in fifo. ? an a/d conversion can be started by - software write 1 to adst bit - external pin stadc ? conversion results are held in data regist ers for each channel with valid and overrun indicators. ? conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion resu lt matches the compare register setting.
m052/m054 data sheet publication release date: mar 15, 2011 - 46 - revision v1.0 ? channel 7 supports 2 input sources: exter nal analog voltage and internal fixed bandgap voltage. ? support self-calibration to minimize conversion error.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 47 - revision v1.0 6.12 external bus interface (ebi) 6.12.1 overview numicro m051 ? series equips an external bus interface (ebi) for external device used. to save the connections between external devi ce and this chip, ebi support address bus and data bus multiplex mode. and, address latch enable (ale) signal supported differentiate the address and data cycle. 6.12.2 features external bus interface has the following functions: 1. external devices with max. 64k-byte size (8 bit data width)/128k-byte (16 bit data width) supported 2. variable external bus base clock (mclk) supported 3. 8 bit or 16 bit data width supported 4. variable data access time (t acc), address latch enable time (tale) and address hold time (tahd) supported 5. address bus and data bus multiplex mode supported to save the address pins 6. configurable idle cycle supported for different access condition: write command finish (w2x), read-to-read (r2r)
m052/m054 data sheet publication release date: mar 15, 2011 - 48 - revision v1.0 6.13 flash memory controller (fmc) 6.13.1 overview m052/m054 equips with 16k/8k bytes on chip embedded flash eeprom for application program memory (aprom) that can be updated through isp/iap procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on cortex-m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro m051 ? series also provide additional 4k bytes data flash for user to store some applicat ion depended data befor e chip power off. 6.13.2 features ? run up to 50 mhz with zero wait state for continuous address read access ? 16/8kb application program memory (aprom) ? 4kb in system programming (isp) loader program memory (ldrom) ? fixed 4kb data flash with 512 bytes page erase unit ? in system program (isp)/in application pr ogram (iap) to update on chip flash eprom ? in circuit program (icp) via serial wire debug interface (swd)
64 m052/m054 data sheet publication release date: mar 15, 2011 - 49 - revision v1.0 7 typical application circuit aa12 ri2c1 4.7k ad0 ri2c2 4.7k ad1 ad2 dvdd rxd0 txd 0 dvdd i2c-eeprom 24lc64 ui2c1 soic8\1.27\5.6mm gnd 4 a2 3 a1 2 a0 1 sda 5 scl 6 wp 7 vcc 8 i2c ad3 eeprom address:0h cb9 0.1 uf dvdd met22 met23 dvdd dvdd miso_1 nss1 p32 uspi1 w25x16vssig soic-8p cs# 1 do 2 wp# 3 gnd 4 di 5 clk 6 hold# 7 vcc 8 spi dvdd rspi1 4.7k rspi2 4.7k cb7 0.1 uf sclk1 mosi _1 sda scl sda ad4 scl nwr ad5 ad12 ad6 ad11 ad10 ad13 ad7 ad14 nticerst avdd ad5 ad6 p40 ale ad7 ad9 ad8 ad3 uart_txd rxd0 txd 1 rxd1 txd 0 s1 sw dip-4 swdip8 1 2 3 4 8 7 6 5 uart_rxd ad4 nrd ad5 ebi d12mo ad6 l1 fb ad7 cb3 0.1 uf cb4 0.1 uf nwr avdd dvdd d12mi dvss cb8 0.1 uf dvss u4 m052_54 lqfp 48 m052_lqfp_48 ain1/t2/p1.1 44 ain 2/rxd1/p1.2 45 ain3/txd1/p1.3 46 ain3/ss0/p1.4 47 p4.2 48 mosi_0/ain5/p1.5 1 miso_0/ain6/p1.6 2 sclk0/ain7/p1.7 3 vss 17 ld o_c ap 18 p2.0/ad 8/pw m 0 19 p2.1/ad 9/pw m 1 20 p2.2/ad 10/pw m 2 21 p2.3/ad 11/pw m 3 22 p2.4/ad 12/pw m 4 23 p4.0 24 p2.6/ad14/pwm6 26 p4.6/ice_clk 30 p4.7/ice_dat 31 p0.7/ad7/sclk1 32 p0.6/ad6/miso_1 33 p0.5/ad5/mosi_1 34 p0.4/ad4/ss1 35 p4.1 36 p0.3/ad 3/rts0 37 p0.2/ad 2/cts0 38 p0.1/ad 1/rts1 39 rst 4 rxd/p3.0 5 avss 6 mclk/int1/p3.3 9 txd / p3. 1 7 int0/p3.2 8 sda/t0/p3.4 10 scl/t1/p3.5 11 p4.3 12 p3.6/w r /c ko 13 p4.5/ale 29 p4.4/cs 28 ain0/t2/p1.0 43 avdd 42 vd d 41 p0.0/ad 0/cts1 40 p3.7/r d 14 xtal1 16 xtal2 15 p2.5/ad13/pwm5 25 p2.7/ad15/pwm7 27 mosi_0 aa15 avss miso_0 sclk0 aa14 avss nticerst aa13 dvss p33 p41 l2 fb aa5 ad4 tic edat adc input tic eclk ale aa6 ncs cb5 0.1 uf dvdd dvdd dvss cb6 0.1 uf dvss ad15 u3 bs616lv4017eg70(tsop-44) a4 1 a3 2 a2 3 a1 4 a0 5 cs 6 i/o0 7 i/o1 8 i/o2 9 i/o3 10 vcc 11 vss 12 i/o4 13 i/o5 14 i/o6 15 i/o7 16 we 17 a17 18 a16 19 a15 20 a14 21 a13 22 nc 28 a8 27 a12 23 a11 24 a9 26 a10 25 i/o8 29 i/o9 30 i/o10 31 i/o11 32 vcc 33 vss 34 i/o12 35 i/o13 36 i/o14 37 i/o15 38 lb 39 ub 40 oe 41 a5 44 a6 43 a7 42 aa7 ad3 cb1 0.1 uf ad2 nrd title size document number rev date: sheet of application.dsn 1.0 m052_54 application circuit 11 thursday , august 19, 2010 c5 10uf tan t-b ad1 ad0 dvdd ad12 ad11 ad10 ad9 ad8 ale ad15 ad14 ad13 cb2 0.1 uf aa10 aa9 aa8 p42 u2 74f373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oe 1 le 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 vcc 20 gnd 10 aa13 aa12 aa11 aa15 aa14 ad15 nss0 ad14 txd 1 ad13 rxd1 ad12 p11 aa4 ad11 aa0 aa3 p43 aa1 ad10 aa2 c3 820pf aa2 ad9 aa3 aa1 aa4 ad8 aa0 aa5 ncs u1 74f373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oe 1 le 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 vcc 20 gnd 10 aa6 adc aa8 ad0 aa7 ad1 ice interface c1 10uf/10v tan t-a dvdd aa9 r1 10k reset circuit ad2 x1 12mhz xta l 3 - 1 c4 20p d12mo c2 20p d12mi crystal aa10 con1 1x2 header 1 1 2 2 uart_txd uart_rxd uart dvdd vdd net4 net5 net40 net3 net9 net8 net6 net7 vss r4 33 net10 r6 33 net12 net13 net11 u5 max232a sop16/150 c1+ 1 v+ 2 c1- 3 c2+ 4 c2- 5 v- 6 t2ou t 7 r2in 8 r2out 9 t2i n 10 t1i n 11 r1out 12 r1in 13 t1ou t 14 gnd 15 vcc 16 aa11 c7 1uf tant-a c6 1uf tan t-a c9 1uf tant-a c8 1uf tan t-a p1 db9-m ( ) db9l-hp 5 9 4 8 3 7 2 6 1 10 11 r3 33 r5 33 icejp1 header 5x2 header5x2 1 2 3 4 5 6 7 8 9 10 nticerst ti c ec lk ti c ed at
m052/m054 data sheet publication release date: mar 15, 2011 - 50 - revision v1.0 8 electrical characteristics 8.1 absolute maximum ratings symbol parameter min max unit dc power supply vdd ?vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v oscillator frequency 1/t clcl 0 40 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of th e device.
64 m052/m054 data sheet publication release date: mar 15, 2011 - 51 - revision v1.0 8.2 dc electrical characteristics (vdd-vss=2.5~5.5v, ta = 25 c, f osc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5v ~ 5.5v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.45 +10% v v dd > 2.7v band gap analog input v bg -5% 1.26 +5% v v dd =2.5v ~ 5.5v analog operating voltage av dd 0 v dd v i dd1 32 ma v dd = 5.5v@50 mhz, enable all ip and pll, xtal=12 mhz i dd2 24 ma v dd =5.5v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 31 ma v dd = 3v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 23 ma v dd = 3v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 17 ma v dd = 5.5v@ 12mhz, enable all ip and disable pll, xtal=12 mhz i dd6 14 ma v dd = 5.5v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd7 16 ma v dd = 3v@12 mhz, enable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd8 13 ma v dd = 3v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd9 12 ma v dd = 5.5v@4 mhz, enable all ip and disable pll, xtal=4mhz i dd10 10 ma v dd = 5.5v@4 mhz, disable all ip and disable pll, xtal=4mhz i dd11 10 ma v dd = 3v@4 mhz, enable all ip and disable pll, xtal=4mhz operating current normal run mode @ 4 mhz i dd12 9 ma v dd = 3v@4 mhz, disable all ip and disable pll, xtal=4 mhz operating current i idle1 19 ma v dd = 5.5v@50 mhz, enable all ip and pll, xtal=12 mhz
m052/m054 data sheet publication release date: mar 15, 2011 - 52 - revision v1.0 i idle2 11 ma v dd =5.5v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 18 ma v dd = 3v@50 mhz, enable all ip and pll, xtal=12 mhz idle mode @ 50 mhz i idle4 10 ma v dd = 3v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 10 ma v dd = 5.5v@12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 7 ma v dd = 5.5v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle7 9 ma v dd = 3v@12 mhz, enable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle8 6 ma v dd = 3v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle9 5 ma v dd = 5.5v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 4 ma v dd = 5.5v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 4 ma v dd = 3v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 3 ma v dd = 3v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pwd1 15 a v dd = 5.5v, no load @ disable bov function standby current power-down mode (deep sleep mode) i pwd2 11 a v dd = 3.0v, no load @ disable bov function input current p0/1/2/3/4 (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5v, v in = 0.4v input leakage current p0/1/2/3/4 i lk -2 - +2 a v dd = 5.5v, 0 64 m052/m054 data sheet publication release date: mar 15, 2011 - 53 - revision v1.0 positive going threshold (schmitt input), /rst v ihs 0.7v dd - v dd +0. 5 v internal /rst pin pull up resistor r rst 40 150 k ? negative going threshold (schmitt input), p0/1/2/3/4 v ils -0.5 - 0.2v dd v positive going threshold (schmitt input), p0/1/2/3/4 v ihs 0.4v dd - v dd +0.5 v i sr11 -300 -370 -450 a v dd = 4.5v, v s = 2.4v i sr12 -50 -70 -90 a v dd = 2.7v, v s = 2.2v source current p0/1/2/3/4 (quasi- bidirectional mode) i sr12 -40 -60 -80 a v dd = 2.5v, v s = 2.0v i sr21 -20 -24 -28 ma v dd = 4.5v, v s = 2.4v i sr22 -4 -6 -8 ma v dd = 2.7v, v s = 2.2v source current p0/1/2/3/4 (push-pull mode) i sr22 -3 -5 -7 ma v dd = 2.5v, v s = 2.0v i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v sink current p0/1/2/3/4 (quasi-bidirectional and push-pull mode) i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brownout voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brownout voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brownout voltage with bov_vl [1:0] =10b v bo3.8 3.7 3.8 3.9 v brownout voltage with bov_vl [1:0] =11b v bo4.5 4.4 4.5 4.6 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5v~5.5v notes: 1. /rst pin is a schmitt trigger input. 2. xtal1 is a cmos input. 3. pins of p0, p1, p2, p3 and p4 can source a transition current when they are being externally driven from 1 to 0. in the cond ition of v dd =5.5v, 5he transition current reaches its maximum value when vin approximates to 2v .
m052/m054 data sheet publication release date: mar 15, 2011 - 54 - revision v1.0 8.3 ac electrical characteristics 8.3.1 external crystal note: duty cycle is 50%. parameter symbol min. typ. max. units condition clock high time t chcx 20 - 125 ns clock low time t clcx 20 - 125 ns clock rise time t clch - - 10 ns clock fall time t chcl - - 10 ns 8.3.2 external oscillator parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 v dd - 2.5 5 5.5 v operating current 12 mhz@ v dd = 5v - 5 - ma 8.3.3 typical crystal application circuits crystal c1 c2 4 mhz ~ 24 mhz optional (depend on crystal specification)
64 m052/m054 data sheet publication release date: mar 15, 2011 - 55 - revision v1.0 figure 8?1 typical crystal application circuit 8.3.4 internal 22.1184 mhz rc oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 mhz +25 c; v dd =5v -1 - +1 % calibrated internal oscillator frequency -40c~+85c; v dd =2.5v~5.5v -3 - +3 % accuracy of un-calibrated internal oscillator frequency -40c~+85c; v dd =2.5v~5.5v -25 - +25 % operating current v dd =5v - 500 - ua 8.3.5 internal 10khz rc oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz +25 c; v dd =5v -30 - +30 % calibrated internal oscillator frequency -40c~+85c; v dd =2.5v~5.5v -50 - +50 % operating current v dd =5v - 5 - ua notes: 1. internal operation voltage comes form ldo.
m052/m054 data sheet publication release date: mar 15, 2011 - 56 - revision v1.0 8.4 analog characteristics 8.4.1 specification of 600khz sps 12-bit saradc parameter sym. min. typ. max. unit resolution - - - 12 bit differential nonlinearity error dnl - 1.2 - lsb integral nonlinearity error inl - 1.5 - lsb offset error eo - +4 10 lsb gain error (transfer gain) eg - +7 1.005 - monotonic - guaranteed - adc clock frequency fadc - - 20 mhz calibration time tcal - 127 - clock sample time ts - 7 - clock conversion time tadc - 13 - clock sample rate fs - - 600 k sps v ldo - 2.5 - v supply voltage vadd 3 - 5.5 v idd - 0.5 - ma supply current (avg.) idda - 1.5 - ma input voltage range vin 0 - avdd v capacitance cin - 5 - pf 8.4.2 specification of ldo & power management parameter min typ max unit note input voltage 2.7 5 5.5 v v dd input voltage output voltage (bypass=0) -10% 2.45 +10% v ldo output voltage output voltage (bypass=1) -10% input voltage +10% v input voltage < 2.7v quiescent current - 100 - ua
64 m052/m054 data sheet publication release date: mar 15, 2011 - 57 - revision v1.0 (pd=0, bypass=0) quiescent current (pd=1, bypass=0) - 5 - ua quiescent current (pd=1, bypass=1) - 5 - ua iload (pd=0) - - 100 ma iload (pd=1) - - 100 ua cbp - 1u - f resr=1ohm cload - 250p - f note: 1. it is recommended that a 10uf or higher c apacitor and a 100nf bypass capacitor are connected between vdd and the cl osest vss pin of the device. 2. for ensuring power stability, a 4.7uf or higher capacitor must be connected between ldo pin and the closest vss pin of the device. al so a 100nf bypass capacitor between ldo and vss help suppressing output noise. 8.4.3 specification of low voltage reset parameter condition min. typ. max. unit operation voltage - 1.7 - 5.5 v quiescent current vdd5v=5.5v - - 5 ua temperature=25 1.7 2.0 2.3 v temperature=-40 - 2.4 - v threshold voltage temperature=85 - 1.6 - v hysteresis - 0 0 0 v 8.4.4 specification of brownout detector parameter condition min. typ. max. unit operation voltage - 2.5 - 5.5 v quiescent current avdd=5.5v - - 125 a
m052/m054 data sheet publication release date: mar 15, 2011 - 58 - revision v1.0 temperature - -40 25 85 bov_vl[1:0]=11 4.4 4.5 4.6 v bov_vl [1:0]=10 3.7 3.8 3.9 v bov_vl [1:0]=01 2.6 2.7 2.8 v brownout voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30m - 150m v 8.4.5 specification of power-on reset (5v) parameter condition min. typ. max. unit reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
64 m052/m054 data sheet publication release date: mar 15, 2011 - 59 - revision v1.0 8.5 spi dynamic characteristics symbol parameter min typ max unit spi master mode (vdd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 26 - - ns t dh data hold time 0 - - ns t v data output valid time - - 10 ns spi master mode (vdd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 39 - - ns t dh data hold time 0 - - ns t v data output valid time - - 16 ns spi slave mode (vdd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - - 2*pclk+40 ns spi slave mode (vdd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+5 - - ns t v data output valid time - - 2*pclk+50 ns
m052/m054 data sheet publication release date: mar 15, 2011 - 60 - revision v1.0 figure 8?2 spi master timing figure 8?3 spi slave timing
64 m052/m054 data sheet publication release date: mar 15, 2011 - 61 - revision v1.0 9 package dimensions 9.1 lqfp-48 (7x7x1.4mm 2 footprint 2.0mm)
m052/m054 data sheet publication release date: mar 15, 2011 - 62 - revision v1.0 9.2 qfn-33 (5x5 mm2, thickness 0.8mm, pitch 0.5 mm)
64 m052/m054 data sheet publication release date: mar 15, 2011 - 63 - revision v1.0 10 revision history version date page description v1.0 mar 15, 2011 - initial issued
m052/m054 data sheet publication release date: mar 15, 2011 - 64 - revision v1.0 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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